Apparatus for allocating and timing a plurality of load intervals

ABSTRACT

Apparatus is disclosed herein for sequentially allocating and timing a plurality of intervals during which different loads are energized within each of a plurality of groups of such intervals. This apparatus includes a common timer circuit associated with all of the groups and having a first timing means for timing a first interval and then providing a first interval termination signal, and second timing means for timing a second interval and then providing a second interval termination signal. The apparatus also includes a common interval sequencer circuit associated with all of the groups and having first actuator means for actuating the second timing means and second actuator means for actuating the first timing means.

United States Patent Hill et a1.

APPARATUS FOR ALLOCATING AND TIMING A PLURALITY OF LOAD INTERVALSCONTROL ea TIMER CONTROL 51 Oct. 17, 1972 Primary Examiner-William C.Cooper Attorney-Meyer, Tilberry and Body [57] ABSTRACT Apparatus isdisclosed herein for sequentially allocating and timing a plurality ofintervals during which different loads are energized within each of aplurality of groups of such intervals. This apparatus includes a commontimer circuit associated with all of the groups and having a firsttiming means for timing a first interval and then providing a firstinterval termination signal, and second timing means for timing a secondinterval and then providing a second interval termination signal. Theapparatus also includes a common interval sequencer circuit associatedwith all of the groups and having first actuator means for actuating thesecond timing means and second actuator means for actuating the firsttiming means.

20 Claims, 7 Drawing Figures GROUP 0R PHASE ON SELECT CIRCUIT PATENTED B171972 3 699 .51 2

SHEET 1. BF 3 FIG. I

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i I L.C.-i 04 FULL -- ACTUATED LOCAL CONTROLLER LC-Z L (DB ON iv A ON ATIMER q) 7 2 SELECT cIRcuIT "W W; 46 is IoRgb OR INVENTORS.

FRANK w. HILL, LARRY K. CLARK a BY PETER e. BARTLETT I (III-:3 TIMERCONTROL Mew 7 3 3 ATTORNEYS PATENTED 17 I973 3.699.512

SHEET 2 BF 3 a 48 v A ON q) 54 g (M GREEN AG 5O No fi T 'WLOAD SWITCH gf GREEN +NOR 56 (DA YELLOW/LS'Z M y :jji NoR p 0+LOAD SWITCH YELLOw NOR1 RED/LS4) AR HQ 5 NOR LOAD SWITCH 5s b 48 4- I N NOR 54 (pa GREEN B6 gjNORgl "TLOAO SWITCH GREEN HNOR 56 OR YELLOW BY I 1 y JHNOR9 LOAD SWITCHYELLOW Lv FIG 4 Mm) SWITCHI FROM TIME CONTROL TC-l, Tc-2 ETC. YELLOW JCLRJTI :1 H FIG. 5 TO 1s (44) j' 4| J E CONTTQBETE-T-ET l /TO IS (46) I w1 HKNTZ i INVENTORS. I 3 FRANK W. HILL, 40 LARRY K. CLARK a l T 1 NORPETER G. BARTLETT I J Mm, 711W, x M,

A'TTORN EYS APPARATUS FOR ALLOCATING AND TIMING A PLURALI'IY F LOADINTERVALS This invention relates to the art of electrical controls and,more particularly, to electrical controls for sequentially allocatingand timing a plurality of load intervals within each of a plurality ofgroups of load intervals. The term load interval" is used in thespecification and claims to designate the interval during which aspecific load is energized such as a red lamp, a yellow lamp, a greenlamp, a turn-arrow lamp and so forth in traffic systems, for example.

The invention is particularly applicable to the art of traffic controland will be described with particular reference thereto; although, it isto be appreciated that the invention has broader applications, such asin process control or other control arts, wherein means are desired forsequentially allocating and timing a plurality of load intervals withineach of a plurality of groups of load intervals.

In the past, past, load interval sequence controllers, such as trafficcontrollers, have frequently incorporated a different timing circuit fortiming each load interval. An electromechanical step switch or anelectronic ring counter has been used to sequentially energize eachtiming circuit in a series fashion. For a large number of intervals tobe allocated and timed, the expense of a correspondingly large number oftiming circuits may be considerable.

In morerecent years, some traffic control circuits, such as thatdisclosed in the US. Pat. to N. A. Bolton, No. 3,251,031 have utilized asingle timer circuit with a different timing I resistor being placed incircuit therewith by a ring counter for each load interval to beallocated and timed. Thus, the ring counter will require one stage foreach resistor to be thus placed in circuit with the timer circuit. Asthe number of load intervals increases in number so does the complexityof such a ring counter. Thus, for example, an eight phase trafficcontroller would require at least sixteen stages, two for each phase toprovide both go and caution intervals, for selecting sixteen differentresistors to be placed in circuit with the timer circuit.

In traffic control applications, as well as other load sequence controlapplications, the various intervals to be allocated and timed may bedivided into groups, each having a plurality of intervals to besequentially allocated and timed. In the eight phase traffic controllerapplication discussed above there are eight groups of intervalsinvolved; to wit, one group per phase. Within each group the sequence isthe same, that is, the go interval is allocated and timed and then acaution interval is allocated and timed.

The present invention is directed toward a load sequence controllerwhich sequentially allocates and times a plurality of load intervalswithin each of a plurality of groups of load intervals without requiringa ring counter, or the like, having one stage for each interval to beallocated and timed.

In accordance with the present invention, apparatus is provided forsequentially allocating and timing a plurality of load intervals withineach of a plurality of groups of load intervals and comprises: a commontimer circuit associated with all of the groups and hav ing first timingmeans for timing a first interval and then providing a first intervaltermination signal and second means for timing a second interval andthen providing a second interval termination signal; and, a commoninterval sequencer circuit associated with all of the groups and havingfirst means for starting the second timing means and a second means forstarting the first timing means.

In accordance with a more limited aspect of the present invention, atimer control circuit is provided for each of the groups, with eachcircuit having first timing control means and second timing controlmeans for respectively controlling the durations of the first intervaland the second interval, and group selection means for selectivelyenergizing one of the timer control circuits.

In accordance with another aspect of the present invention, there isprovided a traffic controller for controlling signal light means for goand caution intervals of at least two traffic phases and comprising: acommon timer circuit associated with all of the traffic phases andhaving go timing means for timing a go interval and then providing a gotermination signal, and timing means for timing a caution interval andthen providing a caution termination signal; and, a common trafficinterval sequencer circuit for all of the traffic phases and havingfirst means for starting the go timing means and second means forstarting the caution timing means.

In accordance with a still more limited aspect of the present invention,the traffic controller further includes a timer control circuit for eachtraffic phase, each circuit having go timing control means and cautiontiming control means for respectively controlling the durations of thego and caution intervals.

In accordance with a still further aspect of the present invention, thetraffic controller includes phase on selection means for selectivelyenergizing one of the timer control circuits.

The primary object of the present invention is to provide an improvedsolid state load sequencer controller which is relatively inexpensive tomanufacture and relatively economical to operate.

Another object of the present invention is to provide an improved solidstate load sequencer circuit for sequentially allocating and timing aplurality of load intervals within a plurality of groups of loadintervals.

A still further object of the present invention is to provide animproved traffic controller for controlling traffic signal lights.

A still further object of the present invention is to provide animproved load sequencer which does not require a ring counter, or thelike, having one stage for each interval to be allocated and timed.

A still further object of the present invention is to provide animproved traffic controller having a common timer circuit and a commontraffic interval sequencer for all of the traffic phases.

These and other objects and advantages of the invention will becomeapparent from the following description of the preferred embodiments. ofthe invention as read in connection with the accompanying drawings, inwhich:

FIG.,1 is a schematic illustration of the invention as applied to atraffic control system incorporating a two phase pretimed trafficcontroller;

FIG. 2 is a combined schematicblock diagram illustration of onepreferred embodiment of the invention;

FIG. 3 is a schematic illustration of load control circuitry forming apart of the invention;

FIG. 4 is a schematic illustration of additional load control circuitryforming a part of the invention;

FIG. 5 is a schematic illustration of the timer circuits found withinFIG. 2;

FIG. 6 is a schematic illustration of the invention as applied to atraffic control system incorporating a two phase full actuated trafficcontroller; and,

FIG. 7 is a combined schematic-block diagram illustration of anotherpreferred embodiment of the invention.

Referring now to the drawings, wherein the showings are for purposes ofillustrating the preferred embodiments of the invention, and not for thepurposes of limiting same, FIGS. 1,2, 3, 4 and 5 illustrate oneembodiment of the invention in the form of a pretimed, two phase trafficcontroller LC-l. This controller serves to control signal light means Sfor sequentially allocating and timing main street (phase A) go andcaution intervals and cross street (phase B) go and caution intervals.The controller, as best shown in FIG. 2, generally comprises: a commontimer circuit T for all of the traffic phases and which includes a gotimer T1 and a caution timer T2; a common traffic interval sequencercircuit IS: a phase A timer control circuit TC-l; a phase B timercontrol circuit TC-2; and, an interval group or phase on select circuitPS.

TIMER CONTROL CIRCUIT Timer control circuits TC-l and TC-2 aresubstantially identical and, accordingly, like components are identifiedwith like character references for simplifying the description of theinvention. The description that follows is given with particular respectto timer control circuit TC-l. As shown in FIG. 2, timer control circuitTC-I includes an NPN transistor having its collector connected to a 8+power supply source and its emitter connected to a go timingpotentiometer 12 and a caution timing potentiometer 14. As shown, thesetwo potentiometers have their resistance portions connected together inparallel between ground and the emitter of transistor 10. The wiper armof potentiometer 12 is coupled through a diode l6, poled as shown, totimer circuit T1. Similarly, the wiper arm of potentiometer 14 isconnected through a diode 18, poled as shown, to timer circuit T2. Itwill be noted that timer control circuits TC-l and TC-2 are connectedtogether in parallel and in the event the controller serves to controlmore than two traffic phases the additional timer control circuits willalso be connected in parallel with timer control circuits TC-l and TC-2.Briefly, whenever transistor 10 in timer control circuit TC-l isactivated into conduction, essentially B+ potential is applied acrossthe resistance portions of potentiometers 12 and 14. The wiper arms onthese two potentiometers are adjusted to provide voltages forapplication to timer circuits T1 and T2, which voltages respectivelycontrol the time duration that these two timers perform their timingfunctions.

COMMON TIMER CIRCUIT The common timer circuit T incorporates a go timerT1 and a caution timer T2, having their inputs respectively coupled tothe commonly connected outputs of all go and caution timingpotentiometers 12 and 14 in the timer control circuits TC-l and TC-2,etc. In addition, another input to timer T1 and to timer T2 is obtainedfrom an output terminal g of sequencer circuit IS. Another input totimer T1 is taken from an output y of sequencer circuit IS.

Reference is now made to FIG. 5 which schematically illustrates timercircuits T1 and T2. As shown there, timer circuits T1 and T2 aresubstantially identical and, accordingly, like components are identifiedwith like reference numbers. The description which follows isspecifically given with reference to timer circuit T1. As shown, timercircuit Tl includes an NPN transistor 20 having its base connected tooutput circuit v of sequencer IS and its emitter connected to ground.The collector to emitter circuit of transistor 20'is connected inparallel with a timing capacitor 22. The junction of the collector oftransistor 20 and one side of capacitor 22 is connected through a timingresistor 24 to a B+ voltage supply source. Capacitor 22 is coupled to acomparator circuit in the form of a differential amplifier, includingtransistors 26'and 28, having their emitters connected together incommon and thence through a resistor 30 to ground. The collectors oftransistors 26 and 28 are respectively connected through resistors 32and 34 to the B+ voltage source. The base of transistor 28 is connectedto the commonly connected cathodes of diodes 16 in timer controlcircuits TC-] and TC-2. The collector of transistor 28 is connected tothe input of a timer memory circuit TM. This timer memory circuitincludes two NOR gates 36 and 38 connected together to define a twoinput bistable multivibrator circuit. The input to the timer memorycircuit from the collector of transistor 28 is taken to the input of NORgate 36. A second input to the timer memory circuit TM is taken fromoutput circuit g of sequencer circuit IS, through a capacitor 40, andthence to one input of NOR gate 38. The output gate 38 serves as theoutput of the timer memory circuit TM and is applied to one input of ANDgate 41.

Timer circuit T2 differs from timercircuit Tl only inasmuch as the baseof transistor 20 is connected to output circuit 3 of sequencer circuitIS and that the base of transistor 28 is connected tothe commonlyconnected cathodes of diodes 18in the timer control circuits TC-l andTC-2. Also, the output of NOR gate 38 in timer circuit T2 is connectedto the second of two inputs of AND gate 41.

PHASE ON SELECT CIRCUIT The phase on select circuit PS, shown FIG. 2,takes the form of a bistable multivibrator circuit having a singletrigger input and two output circuits a and b. Each received triggerpulse, of a negative going polarity, serves to trigger the bistablemultivibrator circuit and shift it from one condition to the other,i.e., to provide a positive potential on either output circuit a or onoutput circuit b. Such multivibrator circuits are well known, oneexample being shown, for instance in US. Pat. application Ser. No.640,654, filed May 23, I967, now Pat. No. 3,466,618. Such amultivibrator circuit may be considered a binary counter, since itserves to count trigger pulses and, in the form of a simple bistablemultivibrator circuit, sequentially energizes output circuits 0, b, 0,etc., with successively received trigger pulses. In the embodimentillustrated, a binary counter capable of counting to two is required forselecting either timer control circuit TC-l or timer control circuitTC-2. In the event, however, a multiphase traffic controller is providedwith, for example, eight phases, the phase on select circuit PS may takeother forms, such as, for example, a binary counter capable of countingto eight.'Also, eight output circuits a, b, etc., would be required,each to be energized in accordance with its decimal number forenergizing an associated timer control circuit. In the event amultistage binary counter is used, some interface equipment, such as abinary to decimal decoder circuit may be required in order to providethe correct number of output circuits.

As shown, however, in FIG. 2, the binary counter or phase on selectcircuit PS has the capability of counting to two to energize outputcircuit a or output circuit b in accordance with the number of pulsesreceived at its input circuit. These pulses are received from the outputof a NOR gate 42 which serves as a signal inverter and has its inputconnected to the output of AND gate 41. Each time AND gate 41 provides abinary 1 signal, representative that both timer T1 and timer T2'havecompleted their timing functions, the output of NOR gate 42 goes from apositive direct current level toward ground potential, and therebyprovides a negative going signal to serve as a trigger pulse fortriggering the phase on select circuit PS from one condition to theother. Output circuits a and b of phase on select circuit PS arerespectively coupled to the base electrodes of transistors in timercontrol circuits TC-l and TC-2. Also, these two output circuits areconnected to output terminals phase A ON and phase B ON.

INTERVAL SEQUENCER CIRCUIT The interval sequencer circuitIS serves tocontrol the sequence of the intervals to be allocated and timed within aparticular group, or in the case of traffic control, within a particularphase. Thus, in a two phase, pretimed traffic controller wherein eachphase is allocated a go signal and then a caution signal, the sequencerserves to ensure that when, for example, the phase A operationcommences, timer Tl completes its timing function before timer T2commences its timing function The sequencer circuit IS may take variousforms and, as shown in FIG. 2, it includes two NOR gates 44 and 46connected together to define a two input bistable multivibrator circuit.One input is taken from the output circuit of timer T1 and is applied tothe input of NOR gate 44. The other input is taken from the output oftimer circuit T2 and is applied to the input of NOR gate 46. The outputof NOR gate 44 is connected to output circuit g. Similarly, the outputof NOR gate 46 is connected to output circuit y.

SIGNAL LIGHT CONTROL CIRCUITS Signal light control circuits are shown inFIGS. 3 and 4 for energizing go, caution and stop signal lightsassociated with phases A and B. Thus, as shown in FIG. 3, a circuit isprovided for energizing the phase A green light AG, or the phase Ayellow light AY, or the phase A red light AR. The circuit includes NORgates 48, 50 and 52 having their inputs respectively coupled to thephase A on circuit (output circuit a) of phase on select circuit PS,output circuit g and output circuit y. NOR gates 54 and 56 each have twoinputs. The inputs of NOR gate 54 are coupled to the outputs of NORgates 48 and 50 and the inputs of NOR gate 56 are coupled to the outputsof NOR gates 48 and 52. The outputsof,

NOR gates 54 and 56 are coupled to the input of a NOR gate 58 as well asto load switches LS-l and LS-2. The output of NOR gate 58 is coupled toload switch LS-3. The outputs of NOR gates 54, 56 and 58 serve totrigger load switches LS-l, LS-2 andLS-3. These load switches may, forexample, take the form of triacs having their gates connected to theoutputs of the associated NOR gates 54, 56 and 58. As is well known,once a positive signal is applied to the gate of such a triac, the triacis gated into conduction for purposes of switching an alternatingcurrent voltage source across a load. Alternating current voltage sourceV is coupled to each of the load switches LS-l, LS-2 and LS-3 which,when gated into conduction by their respective NOR gates, serve tocouple the voltage source across the selected signal light AG, AY or AR.

The circuit illustrated in FIG. 4 is substantially the same as thatshown in FIG. 3 and accordingly like components are illustrated withlike character references. The differences made, however, are that loadswitches LS-l, LS-Z and LS-3 are respectively coupled to phase B lightsBG, BY and BR. Also, the input to NOR gate 48 is coupled to the phase'BON terminal. To avoid confusion, the like components are identified witha primed character reference.

OPERATION OF FIRST EMBODIMENT In the operation of the controller it maybe assumed that output circuit a of phase on select circuit PS FIG. 2)is energized to provide a phase on signal. This is a positive signalwhich serves to forward bias transistor 10 in timer control circuit TC-linto conduction. Thus, potentiometers 12 and 14 apply control potentialsto timer circuits T1 and T2 in the common timer circuit T. During theprevious interval the output circuit y of sequencer circuit IS provideda positive potential to forward bias transistor 20 into conduction toshort circuit timing capacitor 22. However, when timer circuit T2,during that previous interval completed its timing function the outputcircuit y, which is connected to the output of NOR gate 46, became a.binary 0" or ground potential, thereby removing this short circuit.Accordingly, timer circuit T1 commences to time by permitting capacitor22 to charge toward the B+ potential. Since the base of transistor 28(FIG. 5) is coupled to potentiometer 12 in timer control circuit TC-l, apotential as determined by the adjustment of the wiper arm ofpotentiometer 12 is applied between ground and base of transistor 28.When the voltage stored by capacitor 22 exceeds that applied betweenground and the base of transistor 28, transistor 28 will be reversebiased and a positive, i.e., a binary l signal is applied to the inputof NOR gate 36. Thus, the output of NOR gate 36 becomes a binary 0signal causing the output of NOR gate 38 to become a binary 1 signal.This binary l signal is applied to one input of AND gate 41. Also, thisbinary 1" signal is applied to one input of NOR gate 44 in sequencercircuit IS. This de-energizes output circuit 3 and, in turn, causes theoutput of NOR gate 46 to carry a binary l" signal. Since the output ofNOR gate 46 carries a binary l signal, output circuit v is energized tocarry a positive signal. This forward biases transistor 20 in timercircuit T1 to maintain that timer reset by short circuiting capacitor22. Since outsignal at the output of NOR gate 38 and this signal isapplied to the second input of AND gate 41 as well as to the input ofNOR gate 46 in the sequencer circuit IS. This causes the sequencercircuit [S to revert to its original condition wherein output terminal gis energized. Since a binary l signal is received on both inputs of ANDgate 41, its output circuit now applies a binary l signal to the inputof NOR gate 42. NOR gate 42 serves as an inverter and provides anegative trigger pulse to the single input of the phase on-selectcircuit PS, causing its output terminal a to become de-energized and itsoutput terminal b to be energized and carry a phase on signal. So longas a phase on signal is carried by output circuit b of the phase onselect circuit PS, the phase B operation will continue in the samefashion as explained above with reference to the phase A operation.

During the phase A operation described above, the phase A ON terminal isenergized and, at different times, output circuit 3 and output circuit Yof the ,sequencer circuit'IS are energized, During the period thatoutput circuits a and g are energized, the outputs of NOR gates 48 and50 of the circuit shown in FIG. 3

carry binary signals, whereupon the output circuit "energized. Whensequencer output circuit y becomes ,energized during the period that thephase A ON terminal is energized, then the output circuit of NOR gate 56carries a binary l signal for actuating load switch LS-2 into conductionto energize phase A yellow light AY. Whenever thephase A 0N terminal isnot energized or for some reason it is energized but neither outputcircuits 3 nor y is energized, then the output circuits of NOR gates 54and S6 carry binary 0 signals, causing the output circuit of NOR gate 58to carry a binary l signal to actuate load switch LS-3 into conductionto energize the phase A redlight AR.

The operation which ensues during the phase B operation is the same asdescribed above with reference to the phase A operation and no furtherdescription is deemed necessary for a complete understanding of theinvention.

SECOND EMBODIMENT Reference is now made to FIG. 6 which shows a secondembodiment of the invention as applied to a g 7 two phase, full actuatedtraffic controller LC2. This controller, like controller LC-l, serves toallocate and time go and caution signals to phase A and phase B.

' However, both phases A and B are traffic actuated vehicle is detected.Alternatively, the detectors may take the form of presence detectorswhich may be used in a counting operation for providing a pulse for eachdetected vehicle. It is also contemplated that the detectors may takethe form of true presence detectors which provide a presence signal solong as a vehicle is present within a zone of influence. Such presencedetectors may be either loop detectors or ultrasonic detectors, both ofwhich are well known to those skilled in the art.

Reference is now made to FIG. 7 which is quite similar to that circuitshown in FIG. '2, and, ac-

cordingly, like components are identified with like tor circuit includesa detector memory circuit DMl for remembering a traffic detection inphase A and a detector memory circuit DM 2 for remembering a trafficdetection in phase B. It is to be appreciated that such memory circuitryis shown on the premise that the detectors are spot detectors. If thedetectors are presence detectors, then memory circuits DM1 and DM2 maybe eliminated. As shown, however, each of the detector memory circuitsDM1 and DM2 includes a pair of NOR gates 60 and 62 connected together todefine a two input bistable multivibrator circuit. One of the inputs todetector memory circuit DMl is taken from the phase A 0N terminal to oneinput of NOR gate 60. The other input is taken from the output of a NORgate 64 to the input of NOR gate 62 in detector memory DMl. NOR gate 64has its input coupled through a resistor 66 to v the B+ voltagepotential. The junction of resistor 66 and NOR gate 64 is coupled to thenormally open switch DA. Similarly, one input of NOR gate 60 in detectormemory DM2 is connected to the phaseB ON terminal and one input of NORgate 62 in detector memory DM2 is connected to the output of a NOR gate68. .The input to NOR gate 68 is connected to the normally open switchDB as well as through a resistor 70 to a 8+ voltage supply source.

In addition to the foregoing circuitry, the additional circuitry addedin FIG. 7 includes a detector logic circuit DL. This detector logiccircuit includes a NOR gate 72 having its input coupled to the output oftimer circuit T1 and its output coupled to one input each of NOR gates74 and 76, respectively. The output of'detector memory DMl is coupled toone input of NOR gate 74, and, similarly, the output of detector memoryDM2 is connected to one input of NOR gate 76. The output circuits of NORgates 74 and 76 are connected together in common and thence to the inputof NOR gate 44 in the sequencer circuit IS.

OPERATION OF SECOND EMBODIMENT In the description which follows onlythat operation which results from the addition of the detector circuitsadded in FIG. 7 is described, the remaining operational steps havingbeen described hereinbefore with reference to FIG. 2. Briefly, in thisembodiment if a green signal is being allocated to phase A and thetimerlocated to phase A and the controller will automatically be sequenced toallocate and time a green signal to phase B. p

It may be assumed that A has been allocated a green signal and thattimer Tl hascompleted its timing function. Thus, the output circuit oftimer Tl appliesa binary l signal to the input of NOR gate 72 whichinverts the signal to apply a binary 0 signal to the inputs of NOR gates74 and 76. If no vehicle actuation has taken place in phaseB, then abinary 1 signal is applied to the input of NOR gate 68 through resistor70. NOR gate 68, in turn, applies a binary 0 signal to one input of NORgate 62 and its output circuitapplies a binary l signal to the input ofNOR gate .76. Also, it will be noted that since phase B ON terminal isdeenergized, a binary 0 signal is applied to the input of NOR gate 60 indetector memory DM2. Since a binary .1 signal from detector memory DMZis applied to the input of NOR gate 76, the output of that circuitcarries a binary 0 signal which will not cause sequencer circuit is tobe actuatedfrom one condition to the other. If, however, a trafficdetection occurred in phase B, then switch DB would have closed at leastmomentarily to apply a binary 0" signal to the input of NOR gate 68.This momentary pause would have caused the output of NOR gate 68 toapply a binary l signal pulse to the input of NOR gate 62. The output ofNOR gate 62, in turn, would have provided a binary .0-" output whichwould have remained even though detector switch DB provided only amomentary closure. The binary 0 output from detector memory DM2 isapplied to the input of NOR gate '76. Since timer T1 has timed out, theoutput of NOR gate 72 is also a binary 0 signal. Hence, NOR gate 76applies a binary 1 signal to actuate the sequencer is to de-energize itsoutput circuit 3 and energize its output circuit y.Thereafter, timer T2will operate-in a manneras described hereinbefore to time the cautioninterval after which the controller would allocate and time ago intervaltophase B. Theoperation which ensues for phase B is the same asdescribed above with reference to phase A and, accordingly, no furtherdescription is deemed necessary for a complete understanding of theinvention.

Although the invention described in connection with preferredembodiments, it will be readily apparent to those skilled in theart thatvarious changes in form and arrangements of parts may be made to suitrequirements without departing from the spirit and scope of theinvention as definedby the appended claims.

What is claimed is:

1. Apparatus for sequentially allocatingand timing a plurality ofintervals during which different loads are energized within each of aplurality of groupsof intervals, and comprising:

a common timer circuit for all of said groups of intervals having firsttiming means for timing a first interval and then providing a firstintervaltermination signal and second timing means for timing asecondinterval and then providing a second interval termination signal;and t a common interval sequencer circuit for all of said groups ofintervals and having first means for starting said second timing meansin response to a said first termination signal and second means forstarting said first timing means in response to a said secondtermination signal.

2. Apparatus as set forth in claim 1 and including:

a timer control circuit for each said group, each said circuit havingfirst timing control means and second timing control means forrespectively con trolling the durations of the said first interval andsaid second interval.

3. Apparatus as set forth in claim 2 including group selection means forselectively starting one of said timer control circuits.

4. Apparatus as set forth in claim 3 wherein said group selection meansis a binary counter means having outputs 1 through N respectivelycoupled to 1 through N said timer control circuits of N .said groups,said binary counter means having an input for receiving trigger pulseswhereby said outputs 1 through N are sequentially energized forrespectively energizing said 1 through N timer control-circuits.

5. A traffic controller for controlling signal light means during go andcaution intervals for a predetermined number of traffic phases andcomprising:

a phase select circuit capable of being triggered by an input signal andsequentially producing a number of output signals corresponding to thepredetermined number of traffic phases;

a common timer circuit for all of said phases and having go timing meansfor timing a go interval and then providing a go termination signal andcaution timing means for timing acaution interval and then providing acaution termination signal; and

a common traffic interval sequencer circuit for all of said phases andhaving first means for starting said go timing means in response to anyoutput signal from said phase select circuit and second means forstarting said caution timing means in response to said go terminationsignal, said phase select circuit being triggered in response to saidcaution termination signal.

6. A traffic controller as set forth in-claim 5 and including:

a timer control circuit for each said phase, each said circuit having gotiming control meansandcaution timing control means for respectivelycontrolling thedurations of said gointerval and said caution interval.

7. A traffic controller as set forth in claim 6 wherein eachsaid gotiming control means and saidcaution timing control means are adjustablefor adjustingthe-durations of said go intervals and said cautionintervals.

8. A traffic controller for controlling signal light means duringlgo andcaution intervalsfor at least two traffic phases and comprising:

a common timer circuit associated with .all of :said phases andhavinggotiming means fortiming a go interval andthen providing a go terminationsignal and caution'timing meansfor timing a caution in- .terval and thenproviding a cautionterminal signal;

and

a common traffic interval sequencer circuit for all of said phaseshaving first means for starting said go timing means, and

a timer control circuit for each said phase, each said circuit having gotiming control means and caution timing control means for respectivelycontrolling the durations of said go interval and said caution interval,

each said go timing control means and said caution timing control meansbeing adjustable for adjusting the durations of said go interval andsaid caution interval, said adjustable go timing control means andsaidadjustable caution timing control means being each a potentiometerhaving a resistance portion and a movable wiper arm, a movable contactwith said resistance portion, said resistance portions being connectedtogether in parallel, and each said timer control circuit furtherincluding switching means for applying a fixed voltage across each ofsaid resistance portions in that said timer control circuit, whereby thewiper arms associated therewith carry voltages of values determined bythe positions of said wiper arms on said resistance portions.

9. A traffic controller as set forth in claim 8 wherein said go timingmeans and said caution timing means are .respectively coupled to all thesaid potentiometer wiper arms associated with go timing control meansand to all the said potentiometer wiper arms associated with saidcaution timing control means.

10. A traffic controller for controlling signal light means during goand caution intervals for at least two.

traffic phases and comprising:

a common timer circuit for all of said phases and having go timing meansfor timing a go interval and then providing a go termination signal andcaution timing means for timing a caution interval and then providing acaution termination signal; a common traffic interval sequencer circuitfor all of said phases and having first means for starting said gotiming means in response to said caution termination signaland secondmeans for starting said caution timing means in response to said gotermination signal; a timer control circuit for each of trigger'pulsesand at least two output circuits, one for each said phase, which aresequentially energized to respectively carry a phase on signalin'accordance with the number of trigger pulses counted.

V 12. A traffic controller as set forth in claim 11 including triggerpulse means for applying a said trigger pulse to said input each timesaid common timer circuit wherein said triggerpulse means includes anAND circuit inter osed between the input of said binary counter cans andthe said go and cautiontlmmg means in said common timer circuit. 1

14. A traffic controller as set forth in claim 11- wherein said firstand second actuating means in said common interval sequencer circuitrespectively have an output circuit for carrying a go signal forstarting said go timing means and an-output circuit for carrying acaution signal for starting said caution timing means.

15. A traffic controller as set forth in claim 14 including signal lightcontrol means for controlling energization of go, caution and stopsignal lights associated with each said phase, said signal light controlmeans including logic circuit means coupled to said output circuits ofsaid binary counter means and said output circuits of said first andsecond startingmeans in said common interval sequencer circuit forcontrolling energization of the go and caution signal lights associatedwith one phase and the stop signal lights associated with the otherphases in dependence upon which binary counter output circuit isenergized to carry a said phase on signal and which of the sequenceroutput circuits is energized to carry either a said go signal or a saidcaution signal.

16. A traffic controller as set forth in claim 11 wherein each saidtimer control means includes switching means coupled to a different oneof the output circuits of said binary counter means so as to beenergized by a said phase on signal.

17. A traffic controller as set forth in claim 10 wherein said phase onselection means has a plurality of output circuits, one for each saidphase, respectively coupled to an associated one of said timer controlcircuits, each of said output circuits adapted to carry a phase onsignal for energizing its associated one of said timer control circuits.

18. A traffic controller as set forth in claim 17 including trafficdetector circuit means coupled to one of the output circuits of saidphase selection means and adapted to be coupled to detector means fordetecting traffic in a phase associated with said one output circuit forproviding a phase calling signal when traffic is detected bysaiddetector means during a period that a phase on signal is not carried bysaid one output circuit of said phase selection means.

19. A traffic controller as set forth in claim 18 including detectorlogic means associated with at least another of said phases forproviding a sequencer actuation signal only when both a said phasecalling signal and a said go termination signal are concurrentlypresent. I

20. A traffic controller asset forth in 'claim 19 wherein said sequencercircuit second means is coupled to and controlled by said detector logicmeans for starting said cautiontiming means in response to a saidsequencer signal.

' a 12 s a a

1. Apparatus for sequentially allocating and timing a plurality ofintervals during which different loads are energized within each of aplurality of groups of intervals, and comprising: a common timer circuitfor all of said groups of intervals having first timing means for timinga first interval and then providing a first interval termination signaland second timing means for timing a second interval and then providinga second interval termination signal; and a common interval sequencercircuit for all of said groups of intervals and having first means forstarting said second timing means in response to a said firsttermination signal and second means for starting said first timing meansin response to a said second termination signal.
 2. Apparatus as setforth in claim 1 and including: a timer control circuit for each saidgroup, each said circuit having first timing control means and secondtiming control means for respectively controlling the durations of saidfirst interval and said second interval.
 3. Apparatus as set forth inclaim 2 including group selection means for selectively starting one ofsaid timer control circuits.
 4. Apparatus as set forth in claim 3wherein said group selection means is a binary counter means havingoutputs 1 through N respectively coupled to 1 through N said timercontrol circuits of N said groups, said binary counter means having aninput for receiving trigger pulses whereby said outputs 1 through N aresequentially energized for respectively energizing said 1 through Ntimer control circuits.
 5. A traffic controller for controlling signallight means during go and caution intervals for a predetermined numberof traffic phases and comprising: a phase select circuit capable ofbeing triggered by an input signal and sequentially producing a numberof output signals corresponding to the predetermined number of trafficphases; a common timer circuit for all of said phases and having gotiming means for timing a go interval and then providing a gotermination signal and caution timing means for timing a cautioninterval and then providing a caution termination signal; and a commontraffic interval sequencer circuit for all of said phases and havingfirst means for starting said go timing means in response to any outputsignal from said phase select circuit and second means for starting saidcaution timing means in response to said go termination signal, saidphase select circuit being triggered in response to said cautiontermination signal.
 6. A traffic controller as set forth in claim 5 andincluding: a timer control circuit for each said phase, each saidcircuit having go timing control means and caution timing control meansfor respectively controlling the durations of said go interval and saidcaution interval.
 7. A traffic controller as set forth in claim 6wherein each said go timing control means and said caution timingcontrol means are adjustable for adjusting the durations of said gointervals and said caution intervals.
 8. A traffic controller forcontrolling signal light means during go and caution intervals for atleast two traffic phases and comprising: a common timer circuitassociated with all of said phases and having go timing means for timinga go interval and then providing a go termination signal and cautiontiming means for timing a caution interval and then providing a cautionterminal signal; and a common traffic interval sequencer circuit for allof said phases having first means for starting said go timing means, anda timer control circuit for each said phase, each said circuit having gotiming control means and caution timing control means for respectivelycontrolling the durations of said go interval and said caution interval,each said go timing control means and said caution timing control meansbeing adjustable for adjusting the durations of said go interval andsaid caution interval, said adjustable go timinG control means and saidadjustable caution timing control means being each a potentiometerhaving a resistance portion and a movable wiper arm, a movable contactwith said resistance portion, said resistance portions being connectedtogether in parallel, and each said timer control circuit furtherincluding switching means for applying a fixed voltage across each ofsaid resistance portions in that said timer control circuit, whereby thewiper arms associated therewith carry voltages of values determined bythe positions of said wiper arms on said resistance portions.
 9. Atraffic controller as set forth in claim 8 wherein said go timing meansand said caution timing means are respectively coupled to all the saidpotentiometer wiper arms associated with go timing control means and toall the said potentiometer wiper arms associated with said cautiontiming control means.
 10. A traffic controller for controlling signallight means during go and caution intervals for at least two trafficphases and comprising: a common timer circuit for all of said phases andhaving go timing means for timing a go interval and then providing a gotermination signal and caution timing means for timing a cautioninterval and then providing a caution termination signal; a commontraffic interval sequencer circuit for all of said phases and havingfirst means for starting said go timing means in response to saidcaution termination signal and second means for starting said cautiontiming means in response to said go termination signal; a timer controlcircuit for each of said phases, each said circuit having go timingcontrol means and caution timing control means for respectivelycontrolling the durations of said go interval and said caution interval;and phase-on selection means for selectively energizing one of saidtimer control circuits.
 11. A traffic controller as set forth in claim10 wherein said phase on selection means is a binary counter meanshaving at least one input for receiving trigger pulses and at least twooutput circuits, one for each said phase, which are sequentiallyenergized to respectively carry a phase on signal in accordance with thenumber of trigger pulses counted.
 12. A traffic controller as set forthin claim 11 including trigger pulse means for applying a said triggerpulse to said input each time said common timer circuit has successivelyprovided both a said go termination signal and a said cautiontermination signal.
 13. A traffic controller as set forth in claim 12wherein said trigger pulse means includes an AND circuit interposedbetween the input of said binary counter means and the said go andcaution timing means in said common timer circuit.
 14. A trafficcontroller as set forth in claim 11 wherein said first and secondactuating means in said common interval sequencer circuit respectivelyhave an output circuit for carrying a go signal for starting said gotiming means and an output circuit for carrying a caution signal forstarting said caution timing means.
 15. A traffic controller as setforth in claim 14 including signal light control means for controllingenergization of go, caution and stop signal lights associated with eachsaid phase, said signal light control means including logic circuitmeans coupled to said output circuits of said binary counter means andsaid output circuits of said first and second starting means in saidcommon interval sequencer circuit for controlling energization of the goand caution signal lights associated with one phase and the stop signallights associated with the other phases in dependence upon which binarycounter output circuit is energized to carry a said phase on signal andwhich of the sequencer output circuits is energized to carry either asaid go signal or a said caution signal.
 16. A traffic controller as setforth in claim 11 wherein each said timer control means includesswitching means coupled to a different one of the output circuits ofsaid binary counter means so as to be energized by a said phase onsignal.
 17. A traffic controller as set forth in claim 10 wherein saidphase on selection means has a plurality of output circuits, one foreach said phase, respectively coupled to an associated one of said timercontrol circuits, each of said output circuits adapted to carry a phaseon signal for energizing its associated one of said timer controlcircuits.
 18. A traffic controller as set forth in claim 17 includingtraffic detector circuit means coupled to one of the output circuits ofsaid phase selection means and adapted to be coupled to detector meansfor detecting traffic in a phase associated with said one output circuitfor providing a phase calling signal when traffic is detected by saiddetector means during a period that a phase on signal is not carried bysaid one output circuit of said phase selection means.
 19. A trafficcontroller as set forth in claim 18 including detector logic meansassociated with at least another of said phases for providing asequencer actuation signal only when both a said phase calling signaland a said go termination signal are concurrently present.
 20. A trafficcontroller as set forth in claim 19 wherein said sequencer circuitsecond means is coupled to and controlled by said detector logic meansfor starting said caution timing means in response to a said sequencersignal.